{"id":20555,"date":"2024-10-11T15:14:52","date_gmt":"2024-10-11T07:14:52","guid":{"rendered":"https:\/\/www.egistec.com\/?page_id=20555"},"modified":"2024-10-11T15:37:52","modified_gmt":"2024-10-11T07:37:52","slug":"asic","status":"publish","type":"page","link":"https:\/\/www.egistec.com\/zh-hant\/asic\/","title":{"rendered":"ASIC"},"content":{"rendered":"

[vc_row full_width=”stretch_row” bg_type=”bg_color” padding=”medium” vpadding=”medium” sp_top=”80″ sp_bottom=”80″ background_color=”#0069b8″ background_style=”stretch” fixed_bg=”no” enable_parallax=”no” height=”content” bg_overlay_opacity=”0.4″ bg_overlay_dot=”no” triangle_location=”top” css=”.vc_custom_1726041996613{padding-top: 80px !important;padding-bottom: 115px !important;background-color: #0069b8 !important;}”][vc_column]

<\/div>

Design Service & Package Revolution<\/h1><\/div>

\nFrom single-based SoC Package to\u00a0chiplet-based Architectural SoC & Package Solution<\/span>
\n<\/div><\/div>[\/vc_column][\/vc_row][vc_row bg_type=”image” padding=”medium” vpadding=”medium” sp_top=”60″ sp_bottom=”60″ background_style=”stretch” fixed_bg=”no” enable_parallax=”no” height=”content” bg_overlay_opacity=”0.4″ bg_overlay_dot=”no” triangle_location=”top” css=”.vc_custom_1726121538783{padding-top: 80px !important;padding-right: 80px !important;padding-bottom: 80px !important;padding-left: 80px !important;}”][vc_column][vc_column_text css=””]Alcor<\/span><\/a>, the Egis Group* provides chiplet-based architectural SoC and package design services, targeting the booming markets of HPC, datacenters, AI inference, and Large Language Model applications. Regarding key IP of chiplet-based SoC, it definitely includes very high-speed interface IP (e.g, UCIe die-to-die, PCIe chip-to-chip from the Egis Group) and systematic multi-die architecture based on advanced package technologies (e.g., CoWoS and 2.5D\/3D package).
\nAlcor is competent to offer package feasibility analysis at design early stage, which covers single top die to multi-die (e.g., AI die, HBM die) interconnected interposer die.
\nThis one-stop service saves customers time-to-market from design to manufacturing, especially for tsmc CoWoS flow.<\/span><\/p>\n

*Subsidiaries of the Egis.[\/vc_column_text][vc_single_image image=”20551″ img_size=”full” alignment=”center” css=””][\/vc_column][\/vc_row][vc_row full_width=”stretch_row” bg_type=”bg_color” padding=”medium” vpadding=”medium” sp_top=”80″ sp_bottom=”80″ background_color=”#0069b8″ background_style=”stretch” fixed_bg=”no” enable_parallax=”no” height=”content” bg_overlay_opacity=”0.4″ bg_overlay_dot=”no” triangle_location=”top” css=”.vc_custom_1726041996613{padding-top: 80px !important;padding-bottom: 115px !important;background-color: #0069b8 !important;}”][vc_column]

<\/div>

Chiplet-based Architectural SoC by CoWoS<\/h1><\/div><\/div>[\/vc_column][\/vc_row][vc_row bg_type=”image” padding=”medium” vpadding=”medium” sp_top=”60″ sp_bottom=”60″ background_style=”stretch” fixed_bg=”no” enable_parallax=”no” height=”content” bg_overlay_opacity=”0.4″ bg_overlay_dot=”no” triangle_location=”top” css=”.vc_custom_1728616496654{padding-right: 50px !important;padding-left: 50px !important;}”][vc_column][vc_single_image image=”20521″ img_size=”full” alignment=”center” css=””][\/vc_column][\/vc_row][vc_row css=”.vc_custom_1728616464091{padding-right: 50px !important;padding-left: 50px !important;}”][vc_column width=”1\/3″][vc_column_text css=””]<\/p>\n

Chiplet<\/h2>\n
    \n
  • Top die Design Candidates: CPU \/ XPU
    \n\/ AI Accelerator<\/li>\n
  • tsmc CoWoS Rule feasibility analysis<\/li>\n
  • IP\/SoC PPA analysis<\/li>\n
  • HBM Solution Consultant<\/li>\n
  • HBM consigned Flow Management<\/li>\n
  • One-stop top die design service
    \n(spec-in \/ co-sim \/ tape-out \/ manufacturing)<\/li>\n<\/ul>\n

    [\/vc_column_text][\/vc_column][vc_column width=”1\/3″][vc_column_text css=””]<\/p>\n

    Chip on Wafer
    \n(interposer) (CoW)<\/h2>\n
      \n
    • CoWoS Floorplan Architecture Analysis<\/li>\n
    • Interposer Physical Design<\/li>\n
    • Interposer Vendor Option<\/li>\n
    • Interposer Testing<\/li>\n
    • Dummy die Vendor Option<\/li>\n
    • CoW Flow Management<\/li>\n<\/ul>\n

      [\/vc_column_text][\/vc_column][vc_column width=”1\/3″][vc_column_text css=””]<\/p>\n

      On Substrate (oS)<\/h2>\n
        \n
      • Substrate Architecture Design Analysis<\/li>\n
      • Package Design<\/li>\n
      • Package Simulation<\/li>\n
      • Probe Card Wafer Testing<\/li>\n
      • CoWoS Testing<\/li>\n
      • Manufacturing Management<\/li>\n<\/ul>\n

        [\/vc_column_text][\/vc_column][\/vc_row][vc_row full_width=”stretch_row” bg_type=”bg_color” padding=”medium” vpadding=”medium” sp_top=”80″ sp_bottom=”80″ background_color=”#0069b8″ background_style=”stretch” fixed_bg=”no” enable_parallax=”no” height=”content” bg_overlay_opacity=”0.4″ bg_overlay_dot=”no” triangle_location=”top” css=”.vc_custom_1728616288275{margin-top: 80px !important;padding-top: 80px !important;padding-bottom: 115px !important;background-color: #0069b8 !important;}”][vc_column]

        <\/div>

        Arm\u00ae Computing Sub System Chiplet Overview<\/h1><\/div><\/div>[\/vc_column][\/vc_row][vc_row bg_type=”image” padding=”medium” vpadding=”medium” sp_top=”60″ sp_bottom=”60″ background_style=”stretch” fixed_bg=”no” enable_parallax=”no” height=”content” bg_overlay_opacity=”0.4″ bg_overlay_dot=”no” triangle_location=”top” css=”.vc_custom_1726121538783{padding-top: 80px !important;padding-right: 80px !important;padding-bottom: 80px !important;padding-left: 80px !important;}”][vc_column width=”1\/2″ css=”.vc_custom_1728615655071{padding-top: 200px !important;}”][vc_column_text css=””]Establishment of the latest of Arm\u00ae Neoverse\u2122 CSS reference platform, which is the best performance for AI HPC applications.
        \n<\/span>
        \nArm\u00ae CSS platform chiplet Features<\/p>\n
          \n
        • ARM CSS V3 (3nm)<\/li>\n
        • AI Accelerator Die Customization<\/li>\n
        • CoWoS Turnkey Solution<\/li>\n
        • HBM Base Die Design Service<\/li>\n<\/ul>\n

          [\/vc_column_text][\/vc_column][vc_column width=”1\/2″ p_top=”40″ p_bottom=”0″ p_left=”0″ p_right=”0″ bg_overlay_opacity=”0.4″ css=”.vc_custom_1726121516860{padding-top: 40px !important;}”][vc_single_image image=”20509″ img_size=”full” css=””][\/vc_column][\/vc_row]<\/p>\n<\/div>","protected":false},"excerpt":{"rendered":"

          [vc_row full_width=”stretch_row” bg_type=&#…<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-20555","page","type-page","status-publish","hentry","description-off"],"_links":{"self":[{"href":"https:\/\/www.egistec.com\/zh-hant\/wp-json\/wp\/v2\/pages\/20555","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.egistec.com\/zh-hant\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.egistec.com\/zh-hant\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.egistec.com\/zh-hant\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.egistec.com\/zh-hant\/wp-json\/wp\/v2\/comments?post=20555"}],"version-history":[{"count":6,"href":"https:\/\/www.egistec.com\/zh-hant\/wp-json\/wp\/v2\/pages\/20555\/revisions"}],"predecessor-version":[{"id":20563,"href":"https:\/\/www.egistec.com\/zh-hant\/wp-json\/wp\/v2\/pages\/20555\/revisions\/20563"}],"wp:attachment":[{"href":"https:\/\/www.egistec.com\/zh-hant\/wp-json\/wp\/v2\/media?parent=20555"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}