UCIe-A PHY and Controller

Our mass production proven UCIE-A Interconnect Solutions, offer industry-leading power efficiency, performance, and low latency, tailored for the next generation of high-performance computing, AI, and data center applications.

Key Features

Supports CoWoSTM, INFOTM and EMIBTM package technologies

8-channel PHY with 64Tx/64Rx lanes per channel

Industry leading power consumption

End-to-end Latency: 3.5ns@16Gbps

Patented voltage and Temperature Adaptive receiver to compensate VT changes during operation

Real-time per lane data-eye monitor to monitor the health of each lane

Controller supports CXS, AXI and feedthrough

UCIe-S PHY and Controller

Our silicon proven UCIE-S Interconnect IP Solutions, offer industry-leading power efficiency, performance, and low latency, tailored for the next generation of consumer electronics, automotive, high-performance computing, AI, and data center applications.

Key Features

Supports MCM, BGA packages and Chiplet2Chiplet interconnects on PCB

Available process nodes: 28, 22, 16, 12, 7, 6nm

X16 and X32 PHY with bump maps defined in UCIe 2.0 specifications

Industry leading power consumption

Supports speeds: (Depends on channel insertion loss)

  • Grand L: 4, 8, 12 and 16Gbps
  • Grand H: 24 and 32Gbps

Extreme low End-to-end Latency

Patented voltage and Temperature Adaptive receiver to compensate voltage and temperature changes during transmission, result in zero or extreme low BER (Bit-Error-Rate)

Real-time per lane data-eye monitor to monitor the health of each lane real time

UCIe Controller supports all UCIe defined interfaces, AXI and CXS

IPTD2D-A PHY and Controller

Our mass production-proven IPTD2D-A D2D Interconnect IP Solutions offer industry-leading power efficiency, performance, and low latency, tailored for the next generation of high-performance computing, AI, and data center applications. With asynchronous “side-band” signals, the IPTD2D PHY can work at any frequency ranging from 2Gbps to 16Gbps, achieving the best balance between total bandwidth and power consumption.

Key Features

Supports CoWoSTM, INFOTM and EMIBTM package technologies

Supports any speed ranging from 2Gbps to 16Gbps, achieving the best balance between total bandwidth and power consumption

Available process nodes

  • TSMC N5 (Mass production proven)
  • TSMC N4P (Silicon proven)
  • TSMC N3E/N3P (Silicon proven)

8-channel PHY with 64Tx/64Rx lanes per channel

Industry leading power consumption @0.238pj/bit (TSMC N3P process, PRBS31 pattern)

Extreme low End-to-end Latency

Industry leading Beach-front bandwidth

Patented voltage and Temperature Adaptive receiver to compensate voltage and temperature changes during transmission, result in zero or extreme low BER (Bit-Error-Rate)

Real-time per lane data-eye monitor to monitor the health of each lane real time

UCIe Controller supports all UCIe defined interfaces, AXI and CXS